FIG. 12 is a block diagram of a conventional computer graphics apparatus. The apparatus comprises a main memory 101, a bridge 102, a host bus 103, a local bus 104, a microprocessing unit (abbreviated to the MPU hereafter) 106, a cache memory 107 and a graphics subsystem 108. The graphics subsystem 108 includes a rendering controller 109, a pixel buffer 110, a RAMDAC 111 and a raster scan display 112.
The bridge 102 permits data transmission among the main memory 101, host bus 103 and local bus 104. The MPU 106 controls the apparatus as a whole using programs stored in the main memory 101. The cache memory 107, typically composed of a static random access memory, retains partial copies of the programs and data stored in the main memory 101. The MPU 101 generally incorporates a cache memory as well. The incorporated cache memory is called a level 1 cache memory, as opposed to the external cache memory 107 which is called a level 2 cache memory.
The main memory 101 stores data and the programs executed by the MPU 106. The host bus 103 is used to effect data transmission between the MPU 106 and the external cache memory 107. The local bus 104, generally acting independently of the host bus 103, is used for multiple purposes such as connection with LAN (local area network) functions as well as with graphics functions. The local bus 104 may accommodate a large number of connectors for connection with various functional devices. With many functional devices connected to it, the local bus 104 operates at a frequency lower than that of the host bus 103.
The graphics subsystem 108 is connected to the local bus 104 and constituted as follows. The rendering controller 109 primarily controls the pixel buffer 110, and processes data in the pixel buffer 110 in accordance with instructions from the MPU 106. The pixel buffer 110 retains the image data to be displayed on the display 112 in the form of bit data (i.e., digital data) representing the display pixels involved. The RAMDAC 111 converts to analog values (usually voltages) the bit data (digital data) corresponding to the display pixels read from the pixel buffer 110 in keeping with the raster scan on the display 112 to drive it. The raster scan display 112 displays the image data held in the pixel buffer 110 as the bit data.
In the most typical configuration of personal computers marketed in 1995, the MPU 106 is a Pentium.TM. processor from Intel, the host bus 103 is 64 bits wide and operative at 66 MHz, and the local bus 104 is 13 bits wide and operative at 33 MHz.
FIG. 13 is a block diagram of another conventional computer graphics apparatus similar to that of FIG. 12. What characterizes the computer graphics apparatus of FIG. 13 is its constitution specialized to generate three-dimensional images. The setup of FIG. 13 supplements the constitution of FIG. 12 with a texture memory 113 and a Z-buffer 114. The pixel buffer 110, like its counterpart in FIG. 12, holds the image to be displayed on the raster scan display 112 in the form of digital (bit) data. The texture memory 113 is used when a graphic form having a texture is to be rendered; the memory retains data representing the texture of the graphic form surface. The Z-buffer 114 is specific to the process of generating three-dimensional images. This is a buffer that holds the vertical depth (i.e., distance) from the display surface of the bit data representing the pixels (in terms of color intensities) in the pixel buffer 110. The Z-buffer 114 is needed to determine whether any point in the three-dimensional space is to be either hidden by something else and not displayed, or not hidden and displayed (the process is known as hidden-surface removal). Detailed Z-buffer algorithms are discussed illustratively by Foley, van Dam, Feiner and Hughes in "Computer Graphics: Principles and Practice" (published by Addison-Wesley).
Constituted as outlined, the conventional computer graphics apparatus typically requires the pixel buffer memory 110, texture memory 113 and Z-buffer memory 114 in addition to the main memory 101. The resulting increase in total memory usage entails higher cost. Furthermore, the MPU 106 conventionally needs to be supplemented by the rendering controller 109 that processes the content of the pixel buffer 110. With more logic functions such as arithmetic circuits additionally included, the system tends to comprise more logic chips of higher capacities leading to a further cost increase.